1. Field of the Invention
The present invention relates generally to power-up reset circuits, and more specifically to CMOS power-up reset circuits which provide a signal indicating that the power supply voltage applied to such a circuit exceeds a predetermined value.
2. Description of Related Art
Power-up reset circuits are frequently utilized in electronic systems for ensuring predictable operation after a system power-up. In some cases, a power-up reset circuit may generate a reset pulse after its applied power supply voltage has reached a safe operating value, which is then used to reset external circuits. These external circuits may be integrated together with the power-up reset circuit upon the same integrated circuit, or may be fabricated external to the power-up reset circuit. In other cases, a power-up reset circuit may provide a signal which disables operation of external circuits until the power supply voltage has reached a safe operating voltage. For example, such a signal can be applied to the asynchronous reset input of a flip-flop, or applied to an output disable input of a clock generator. After the system power supply reaches a predetermined level, this disabling signal generated by such a power-up reset circuit is then removed, thereby enabling the operation of the external circuits. In this way, external circuits are prevented from operation during times when the system power supply provided to those external circuits is below a voltage necessary to ensure adequate and reliable operation of the external circuits.
Frequently, power-up reset circuits have utilized resistor and capacitor time constant techniques to generate a reset signal after a delay governed by the associated RC time constant. Such circuits often incorporate large valued resistors and/or large valued capacitances, which require significant area to implement using most typical integrated circuit processes. Furthermore, these techniques are problematic if the slew rate of the power supply is comparable to, or slower than, the chosen RC time constant. In such cases, the power-up reset circuit will likely enable the external circuits prematurely. Alternatively, if the RC time constant is chosen to be very long, the power-up reset circuit may introduce an unnecessary and a disadvantageously long delay before the external circuits are enabled. A power-up reset circuit which requires no large RC time constants advantageously consumes less area in most implementations.
Power-up reset circuits which trip reliably at a particular predetermined value of a power supply, irrespective of the rise time of that supply, are more suitable for predictably enabling external circuits after the system power supply has reached an adequate voltage, while not introducing arbitrary and lengthy delays after reaching that value.
Historically, many power-up reset circuits have also consumed power after the power supply has fully stabilized at an operating voltage. For large systems with non-critical power requirements, this power dissipation is not problematic. However, in a battery powered system, even a minor amount of DC power consumed by a power-up reset circuit after system power-up can materially limit the battery operating time of the system. A power-up reset circuit which disables static or DC current flow after providing the power-up reset signal advantageously eliminates this unnecessary power dissipation after power-up.
In some instances, a power-up reset circuit exhibiting a hysteresis characteristic is advantageous for providing a power-up signal only after the power supply voltage has initially reached a safe operating voltage threshold, but which will not be re-asserted if the power supply voltage momentarily dips below that same safe operating voltage threshold. Such a dip can occur as a result of noise on a power supply conductor as might occur during a switching transient.
The power supply voltage at which a power-up reset circuit asserts a power-up signal is advantageously determined by ratios of similar or like circuit components and is advantageously relatively insensitive to variations in semiconductor parameters. Such a circuit advantageously requires as few critical sizes or ratios as possible to set this predetermined value of the necessary power supply voltage. Furthermore, it is an advantage for the circuit to be adjustable to include a predetermined voltage suitable for 3 volt operation (e.g., 2.0-2.5 volts), particularly for battery operation of the circuit.